Penerangan: ATMEL SYNARIO VERILOG SIM OPTION
Penerangan: INTEGRAPH SCHEM SYNTH/SIM LIBRA
Penerangan: INTEGRAPH SCHEM SYNTH/SIM LIBRA
Penerangan: EXEMPLAR SYNTHESIS LIBS/INTRFC
Penerangan: DESIGN SYS PWRVIEW/SIMUL 20K GAS
Penerangan: INTEGRAPH SCHEM SYNTH/SIM MAINT
Penerangan: SYNOPSYS LIBRARIES/INTRFC MAINT
Penerangan: SYNOPSYS LIBRARIES/INTRFC MAINT
Penerangan: MAINT FPGA 20K GA VIEWLOGIC SYS
Penerangan: ATMEL SYNARIO BASIC PACKAGE
Penerangan: MENTOR V8 LIBRARIES/INTERFACE
Penerangan: EXEMPLAR SYNTHESIS LIBS/INTRFC
Penerangan: MAINT 20K VIEWLOGIC UPGRADE
Penerangan: MAINT FPGA SCHEMATIC VWLOGIC SYS
Penerangan: CADENCE LIRARIES/INTRFC MAINT
Penerangan: MAINT FPGA 10K GA VIEWLOGIC SYS
Penerangan: ATMEL SYNARIO VHDL SYNTHESIS OPT
Penerangan: MAINT 10K VIEWLOGIC UPGRADE
Penerangan: CADENCE VERILOG LIB/INTRFC MAINT